Wireless communications products and other modern electronic devices typically process and generate both digital and analog signals. To perform their intended functions, these systems often convert analog signals into digital signals, referred to as analog to digital (A/D) conversion. Accordingly, these systems require circuitry to interface signals from the analog domain to signals in the digital domain so that they may perform further digital signal processing. In particular, analog to digital conversion systems (A/D converters, or ADCs) are needed to interface the analog and digital domains.
Advances in wireless communications devices, DVD systems, and other related technologies indicate a need for increased sampling/conversion rates in analog-to-digital conversion systems, along with high resolution. At the same time, however, power consumption is an important design consideration, wherein portable devices need to perform high-resolution analog to digital conversions while consuming a minimal amount of power. Other important performance parameters for A/D converters include differential nonlinearity (DNL) and bandwidth, where the system conversion speed are improved with increased bandwidth. In the past, “flash” type A/D converters have been employed where fast conversions are needed. Flash converters provide a multi-bit digital output value in a single conversion cycle. However, flash converters require a large number of comparator circuits. As a result, flash type converters occupy a large amount of area in an integrated circuit, and also consume a relatively high amount of power.
Pipelined converters attempt to reduce die area and power requirements while sacrificing some conversion speed for high-resolution A/D conversion, wherein 2-4 bit flash type A/D converter stages are cascaded to provide high-resolution conversion. FIGS. 1A-1C illustrate a conventional pipelined A/D conversion system 10 that includes an integer number “X” cascaded flash type subconverter stages 12, with a sample and hold (S/H) circuit 14 coupled to the first subconverter stage 12 to sample an analog input 32. A digital correction unit 18 is coupled to receive a digital output 20 from each of the flash converter stages 12 and provides conversion timing control signals 16 to the stages 12. In this pipelined design, an N-bit binary digital output 22 is produced corresponding to the analog input 32 in X conversion cycles, wherein each stage 12 receives an analog input and provides an M-bit binary digital output 20 and a residue output 44. The digital correction unit 18 receives intermediate M-bit digital signals 20 from each subconverter stage 12 and generates a composite digital output 22 of N bits.
FIG. 1B illustrates one subconverter stage 12 of the A/D system 10, having an M-bit flash AID converter 36, and an M-bit digital to analog (D/A) converter 38 receiving the binary digital output 20 from the A/D converter 36, and generating an analog output 40. A summation circuit 42 receives the analog output 40 of the D/A converter 38, as well as the stage input 32,44, and generates an output signal 34 representing the difference between the stage input 32,44 and the D/A output 40. The difference or error signal 34 is then amplified by an amplifier 46 to provide a stage residue output signal 44 that is provided to the next cascaded flash converter stage 12. Because the residue output 44 corresponds to the remainder signal that cannot be resolved by the M-bit stage 12, the gain for the amplifier 46 is set to 2(M-1), such that the input signal 44 uses the full range of the subsequent stage 12.
FIG. 1C further illustrates the M-bit flash type A/D converter 36 of the stage 12, comprising a resistive voltage divider 50 generating 2M reference voltages between first and second references V+ and V−, respectively. The reference voltages are supplied as first inputs to a corresponding set of 2M comparators 52, with the stage input 32,44 being simultaneously applied to the second comparator inputs. The digital output 20 is determined as an M-bit binary representation 20 of the stage input voltage 32, 44 using output logic 54. The comparators 52 are typically fabricated using metal oxide semiconductor (MOS) transistors to achieve relatively high switching speeds and lower power consumption than bipolar designs. However, these conventional pipelined flash converter systems 10 still occupy a relatively large amount of die area, due at least in part to the provision of 2M comparator circuits 52 in each stage 12, and the system 10 consumes a considerable amount of power. Accordingly, there remains a need for A/D converters that provide high output resolution fast conversions with low DNL, while consuming little power and taking up little space.